To be able to synthesise a HDL file for real hardware, the following functions/datatypes are not allowed:

• datatype time
• statement wait and after
• function rising_edge() (except on the CLK signal)
• function falling_edge() (except on the CLK signal)
• function 'event (except on the CLK signal)

In addition, the following rules should be applied:

• In an asynchronous process (not based on CLK), every signal which stands on the right side of any assignment, has to be in the sensitivity list.
• Always try to use variables instead of signals for internal "variables".

Detailed information about the VHDL support for synthesis can be found in this document (chapter 5): Vivado Synthesis user Guide